1. Field of Invention
The present invention relates generally to a method and system for synthesizing a circuit design. More particularly, the invention relates to a method and system for concurrently synthesizing different parts of a circuit design (blocks) by using budgeting techniques to determine a feasible floor plan for the blocks and perform timing and logic design rules constraints allocation to the blocks.
2. Discussion of Background
Most conventional synthesis tools available to designers are able to handle circuit designs whose size can be up to predetermined number of gate equivalents (100,000, for example). A designer working on a chip with greater than the predetermined number of gate equivalents has to manually partition the circuit design into smaller pieces (e.g., sub-blocks) in order for conventional synthesis tools to operate on the entire circuit design. In addition, partitioning may also be performed to allocate block design tasks to different teams, breaking the circuit design project into smaller, more manageable components. A design with sub-blocks is also referred to as a hierarchical design. Partitioning the circuit design into small sub-blocks is a common procedure for designers and allows conventional synthesis tools to synthesize the entire circuit design.
However, in the above procedure, it is difficult to convert the timing and logic design rules constraints from a top-level view of the chip into local constraints applied to the sub-blocks. The local budgeted constraints are the result of an allocation which provides a nominal timing performance to the sub-blocks. Allocation of timing and logic design rules is needed in order to load the sub-blocks in the synthesis tools and run several sub-block synthesis (eventually in parallel) instead of one full synthesis run on the whole design.
The operation of converting global constraints into local constraints applied to a sub-block is referred to as the characterization of the corresponding sub-block. The operation of converting the global constraints into budgeted local constraints is referred to as the timing and logic design rules constraints allocation.
The timing and logic design rules constraints allocation to a sub-block is useful when a team leader would like to assign each of his engineers to the synthesis of one sub-block. The engineers will work in parallel and each of them will need the timing and logic design rules constraint allocated to his respective sub-block. In this situation, the timing and logic design rules constraints allocation of the sub-blocks should provide the scripts of the synthesis. As a result, this operation has to be done before the synthesis itself.
For a more detailed discussion of the above situation with respect to RTL Floorplanner tools, reference is made to co-pending U.S. application Ser. No. 08/921,361, titled xe2x80x9cMethod and System for Floorplanning a Circuit Design at a High Level of Abstraction,xe2x80x9d filed on Aug. 29, 1997, the content of which is hereby incorporated by reference in its entirety.
Allocation of timing can be performed arbitrarily, simply assigning an amount of total time to each of the blocks or sub-blocks, evenly dividing the total time between blocks, or allocation based on a formula. One example of timing allocation from global constraints to local block/sub-block constraints is provided by Ginetti et al., U.S. Pat. No. 6,086,621 (""621), which is incorporated herein by reference, in its entirety. In Ginetti (""621), allocation of timing budgets is taught using a formula taking into account path lengths of actual and budgeted gates. However, each of the known timing allocation techniques to sub-blocks, whether arbitrary, evenly distributed, or by formula, are not accurate, causing some blocks to be under-constrained, and others to be over-constrained.
The present inventor has realized that high level circuit designs (RTL, for example) from which block placement, interblock timing, etc., are in need of better budgeting, particularly in the early phases of circuit design so that feasible floorplans and timing constraints within and between blocks can be allocated.
The present invention provides a Physical Budgetor that produces a feasible budgeted optimal floorplan out of an RTL description and determines a set of timing constraints for blocks of the floorplan. The floorplan is a set of placed physical blocks, placed physical block i/o, placed external i/o, global routed top level wire, and correspondence between the physical blocks and an initial logical hierarchy. The Physical Budgetor also generates a set of budgeted constraints for each block. These budgeted constraints correspond to a timing estimation and distribution performed by the Physical Budgetor when generating the floorplan. By feasible, we mean that classical synthesis and Place and Route (PandR) tools should be able to implement the RTL description within that floorplan while respecting the timing constraints. If the timing constraints are too tight, the Physical Budgetor advises the user on candidates for modification (modify some RTL descriptions or give up some timing constraints, for example). By optimal, we mean that floorplan should be as small as possible. In one embodiment, the Physical Budgeter produces the floorplan from an RTL description and some constraints, using the following steps:
1) estimate the complexity of the RTL description;
2) perform a physical partitioning, that is generate a list of interconnected physical blocks out of a hierarchical netlist of RTL cells;
3) perform a block placement;
4) perform block i/o placement and top level global routing; and
5) verify that the floorplan is likely to be feasible.
Each of the above steps are performed via the Physical Budgetor, a single tool, having a global view of block timing/global timing and floorplanning, where each of the CPU intensive steps are replaced by fast and accurate estimators (during initial estimation and beginning iterations).
Once the blocks are placed, the present invention performs allocation of timing between the various blocks determining a solid estimate of timing required to implement the block. The timing allocation is determined by identifying logic cones from gates of an un-optimized netlist produced from the RTL. The logic cones are then used to adjust timing and determine a basic high level optimization of the gates, resulting in a solid approximation of block timing. Then, a portion of the global timing constraints are allocated to each block based on the approximate block timing. A similar process is applied to estimate RTL complexity and partition the blocks.
The invention may be embodied in a method of determining a budgeted floorplan of a circuit, comprising the steps of, initializing timing of said circuit, performing a physical budgeting of said circuit, partitioning said circuit into blocks of gates, identifying placement of said blocks, and budgeting time to each of said blocks. The invention also includes budgeting time to each of the blocks, which may be performed by a method of allocating global timing constraints of a circuit across blocks of said circuit, comprising the steps of providing an RTL or other high level description of each block, developing an un-optimized netlist for each sub-block from said RTL, producing a set of logic cones from the un-optimized netlist for each block that identify timing arcs within each block, optimizing the timing arcs within each block using said logic cones, and allocating said global timing constraints to each block based on the optimized timing arcs in each block.
The present invention provides many advances over prior systems, including, but not limited to, a powerful and accurate flexible timing model to model the timing behavior of the combinatorial pieces of the initial RTL description; capability to run a real timing driven partitioning before entering the long synthesis iterations; capability to run a real timing driven block placement before entering the long synthesis iterations; capability to run a real top level net global routing before entering the long synthesis iterations; and capability to run a real timing driven top level buffer insertion before entering the long synthesis iterations. The various processes and techniques of the present invention are described herein with reference to commands available as implemented in a tool (Integration Ensemble) for performing circuit synthesis. However, it should be understood that each of the processes discussed herein may be applied in different types of tools individually or in combination with other processes or devices.